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IDT74ALVCH16825 3.3V CMOS 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT BUFFER/ DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
FEATURES: DESCRIPTION:
IDT74ALVCH16825
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
* High Output Drivers: 24mA * Suitable for heavy loads
This 18-bit buffer/driver is built using advanced dual metal CMOS technology. The ALVCH16825 improves the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as two 9-bit buffers or one 18-bit buffer, and provides true data. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all nine affected outputs are in the high-impedance state. The ALVCH16825 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16825 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
* 3.3V high speed systems * 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1O E1 1O E2
1 56
2O E1 2O E2
28 29
1A1
55
2
1Y1
2A 1
41
16
2Y1
TO EIGHT OTH ER C HAN NELS
TO EIGH T OTHER CHANN ELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c)1999 Integrated Device Technology, Inc.
APRIL 1999
DSC-4546/1
IDT74ALVCH16825 3.3V CMOS 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND -0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100 VTERM(3) TSTG IOUT IIK IOK ICC ISS
Unit V V C mA mA mA mA
1OE1 1Y1 1Y2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OE2 1A1 1A2
GND
1Y3 1Y4
GND
1A3 1A4
VCC
1Y5 1Y6 1Y7
VCC
1A5 1A6 1A7
GND
1Y8 1Y9
GND
1A8 1A9
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT COUT Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
GND GND
2Y1 2Y2
GND GND
2A1 2A2
GND
2Y3 2Y4 2Y5
NOTE: 1. As applicable to the device type.
GND
2A3 2A4 2A5
PIN DESCRIPTION
Pin Names xOEx xAx xYx Data Inputs(1) 3-State Outputs Description Output Enable Inputs (Active LOW)
VCC
2Y6 2Y7
VCC
2A6 2A7
NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
GND
2Y8 2Y9 2OE1
GND
2A8 2A9 2OE2
FUNCTION TABLE (EACH 9-BIT SECTION)(1)
Inputs xOE1 xOE2 L L X H xAx L H X X L L H X Output xYx L H Z Z
SSOP/ TSSOP/ TVSOP TOP VIEW
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance
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IDT74ALVCH16825 3.3V CMOS 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 -1.2 -- 40 V mV A A A A V Unit V
Quiescent Power Supply Current Variation
--
--
750
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 - 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
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IDT74ALVCH16825 3.3V CMOS 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 16 4 VCC = 3.3V 0.3V Typical 18 6 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(O) Parameter Propagation Delay xAx to xYx Output Enable Time xOEx to xYx Output Disable Time xOEx to xYx Output Skew(2) -- -- -- -- -- 500 ps 1.2 5.6 -- 4.9 1.3 4.5 ns 1 6 -- 5.7 1 4.7 ns Min. 1 Max. 4.1 VCC = 2.7V Min. -- Max. 3.9 VCC = 3.3V 0.3V Min. 1 Max. 3.4 Unit ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2 Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVCH16825 3.3V CMOS 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50 VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
ALVC Link
VCC 500 Pulse Generator
(1, 2)
VLOAD Open GND
VIN D.U.T. RT
VOUT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Link
INPUT
tPLH1
tPHL1
VIH VT 0V VOH VT VOL VOH VT VOL
Set-up, Hold, and Release Times
OUTPUT 1
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
tSK (x)
tSK (x)
OUTPUT 2 tPLH2 tPHL2
VT
ALVC Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
ALVC Link
Pulse Width
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVCH16825 3.3V CMOS 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
ALVC X IDT XX Bus-Hold Temp. Range XXX Family XX XXX Device Type Package
PV PA PF 825 16 H 74
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 18-Bit Buffer/Driver with 3-State Outputs Double-Density, 24mA Bus-Hold -40C to +85C
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